As is well known in the field of integrated circuit design, layout and fabrication, the manufacturing cost of a given integrated circuit is largely dependent upon the chip area required to implement desired functions. The chip area, in turn, is defined by the geometries and sizes of the active components such as gate electrodes in metal-oxide-semiconductor (MOS) technology, and diffused regions such as MOS source and drain regions and bipolar emitters and base regions.
Device structures are constantly being proposed with the objective of producing higher response speeds, higher device yields and reliability, lower power consumption and higher power handling capability. Many of the device improvements are achieved by scaling down or miniaturizing the devices. One approach is to simply scale down all process variables, dimensions and voltages. This approach includes, among other factors, for example for the typical MOS device, scaling dielectric thicknesses, channel lengths and widths, junction widths and doping levels. With this approach, the number of devices per unit area increases, threshold voltages decrease, delay time across channels decreases and power dissipated per area decreases. All device parameters, however, do not need to be scaled by the same constant. A design or process engineer may scale some device parameters independently of others which would optimize device operation. This more flexible approach would allow for a choice in geometries to fit with various tradeoffs for device optimization, rather than choosing a more strict scaling approach.
In addition to the geometries and sizes of active components and the ability to scale process variables, the chip area also depends on the isolation technology used. Sufficient electrical isolation must be provided between active circuit elements so that leakage current and low field device threshold voltages do not cause functional or specification failures. Increasingly more stringent specifications, together with the demand, for example, for smaller memory cells in denser memory arrays, places significant pressure on the isolation technology in memory devices, as well as in other modern integrated circuits.
A well-known and widely-used isolation technique is the local oxidation of silicon to form a field oxide region between active areas, commonly referred to as LOCOS. The LOCOS process was a great technological improvement in reducing the area needed for the isolation regions and decreasing some parasitic capacitances. In LOCOS, an oxidation barrier (generally silicon nitride) is placed over the locations of the surface of the chip into which the active devices are to be formed (i.e., the active regions). The wafer is then placed in an oxidizing environment, generally in steam at a high temperature such as 1100.degree. C. The portions of the wafer surface not covered by the oxidation barrier oxidize to form thermal silicon dioxide, with oxidation masked from the active regions by the oxidation barrier. LOCOS field oxide is generally formed to a sufficient thickness that a conductor placed thereover will not invert the channel thereunder, when biased to the maximum circuit voltage.
While LOCOS isolation is widely-used in the industry, it is subject to certain well-known limitations. A first significant limitation of LOCOS is the lateral encroachment known as "birdbeaking", of the oxide into the active areas, due to oxidation of silicon under the edges of the nitride mask. The expected distance of such encroachment must be considered in the layout of the integrated circuit; as such, the chip area is expanded as a result of the encroachment. Of course, the encroachment may be reduced by reducing the field oxide thickness, but at a cost of reduction of the threshold voltage of the parasitic field oxide transistor, and thus reduction of the isolation provided.
In addition, conventional LOCOS isolation adds topography to the integrated circuit surface. The additional topography results from the silicon dioxide necessarily occupying a greater volume than that of the silicon prior to its oxidation, due to the reaction of the oxygen therewith. As a result, the upper surface of conventional LOCOS field oxide lies above the surface of the active regions, with approximately half of the LOCOS field oxide thickness being above the active region surface. This topography requires overlying conductors to cover steps at the edges of the field oxide which, as is well known, presents the potential for problems in photolithography and in etching the conductor layer (i.e., the presence of filaments) and in the reliability of the conductor layer. In addition, the depth of field for submicron photolithography can be exceeded by the topography of the wafer surface.
An additional result with conventional LOCOS is the creation of undesired nitride spots forming along the interface of the silicon substrate and silicon oxide regions, known as the "Kooi" effect. Thermally grown gate oxides formed subsequent to the formation of the field oxide are impeded in the region of these nitride spots. Typically, these nitride spots are removed before gate oxides are formed, as with the well-known sacrificial oxide process as described more fully in U.S. Pat. No. 4,553,314 issued on Nov. 19, 1985 to Chan et al. However, this process of removing the nitride spots increases complexity and thus additional manufacturing costs as well as adding additional topography to the wafer causing step coverage problems at later stages.
A recent isolation technique uses trenches etched into the surface of the wafer at the isolation locations, which are subsequently filled with a thermal or deposited oxide. Such trench isolation can provide extremely thick isolation oxides which extend into the wafer surface with little or no encroachment, and which can have an upper surface which is relatively coplanar with adjacent active regions. An example of such trench isolation is described in U.S. Pat. No. 4,958,213, where a relatively deep trench is etched and subsequently filled with both deposited oxide and thermal oxide. It should be noted, however, that the etching of deep trenches is a relatively expensive process, and one which is quite difficult to perform while maintaining close geometries. In addition, it is well known that thermally formed silicon dioxide; the formation of thermal oxide in trenches, however, causes stress in the silicon, due to the volume expansion of silicon dioxide from that of the silicon prior to its oxidation. As a result, trench isolation tends to rely on deposited oxide to a large degree.
By way of further background, U.S. Pat. No. 4,842,675 describes a method of forming thermal LOCOS field oxide in combination with trenches. According to this method, recesses are etched into the surface of the wafer at the desired locations. A conformal layer of silicon nitride is deposited thereover, followed by deposition of a thicker layer of silicon oxide. The deposited silicon oxide is etched back to expose the silicon nitride at the bottom of the wider isolation locations, but not within the narrower isolation locations. The exposed nitride is etched away, the deposited silicon oxide is removed, and the exposed single crystal portions of the wafer are thermally oxidized in conventional LOCOS fashion. The remainder of the volume of the isolation locations are filled with deposited oxide, after the formation of the thermal oxide. It should be noted, however, that the availability of silicon for such oxidation is limited to that at the bottom surface of the wider recess. In addition, the process appears to be quite complex.
By way of further background, U.S. Pat. No. 5,130,268 describes a method of forming isolation structures into relatively shallow recesses etched into a surface of an integrated circuit. After the formation of the recesses, sidewall filaments of insulating material are formed into some or all of the recesses, exposing the bottom silicon portion of the recess. Selective epitaxy then forms a silicon layer within the recesses from the bottom up, but not along the sides. The selective epitaxial layer is oxidized so that the recesses are substantially filled with thermal silicon dioxide.
It is therefore an object of the present invention to provide a method of forming an isolation structure have a surface which is substantially coplanar with the surface of the adjacent active regions.
It is a further object of the present invention to provide such a method which utilizes thermal silicon dioxide as the isolation material.
It is a further object of the present invention to provide such a method which utilizes relatively shallow trenches in the surface of the wafer.
It is a further object of the present invention to provide such a method which substantially fills the isolation recesses with thermal silicon dioxide.
It is a further object of the present invention to provide such a method which can be used for both wide and narrow isolation locations.
It is a further object of the present invention to provide such a method which utilizes standard semiconductor processes.
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification together with the drawings.